The present invention relates to a semiconductor memory device having memory cells arranged in a matrix, in which each of the memory cells includes a ferroelectric capacitor for storing binary data using displacement of polarization of a ferroelectric film and a selection transistor for selecting the ferroelectric capacitor for data read/write, and a drive method for such a semiconductor memory device.
A conventional semiconductor memory device having memory cells each including a ferroelectric capacitor and a selection transistor arranged in a matrix will be described with reference to FIG. 9.
FIG. 9 shows four memory cells MC00, MC01, MC10 and MC11, for example, arranged in a matrix of two rows and two columns. This conventional semiconductor memory device has a 2T2C structure, in which the memory cell MC00, for example, includes two ferroelectric capacitors C0 and C1 and two selection transistors Q0 and Q1. One of paired electrodes of each of the ferroelectric capacitors C0 and C1 is connected to the drain of the corresponding selection transistor Q0 or Q1.
Bit lines BL0 and XBL0 constitute a bit line pair, and bit lines BL1 and XBL1 constitute another bit line pair. The bit lines BL0 and XBL0 are connected to the sources of the corresponding selection transistors Q0 and Q1, respectively.
Word lines WL0 and WL1 are connected to the gates of the selection transistors of the memory cells arranged in the word line direction.
Cell plate lines CP0 and CP1 are connected to the other electrode of each of the ferroelectric capacitors of the memory cells arranged in the word line direction.
A sense amplifier SA0 is connected to the bit line pair BL0 and XBL0 and also connected to a pair of data bus lines DL0 and XDL0. A sense amplifier SA1 is connected to the bit line pair BL1 and XBL1 and also connected to a pair of data bus lines DL1 and XDL1.
Data write/read operation of the semiconductor memory device shown in FIG. 9 will be described. Assume that data is to be written in and read from the memory cell MC00, as an example.
Data write operation is achieved by writing complementary data in the two ferroelectric capacitors of the memory cell in which the data is to be written. A high voltage is applied to the word line WL0 to turn on the selection transistors Q0 and Q1, and then voltages of the opposite polarities are applied between the cell plate line CP0 and the bit line BL0 and between the cell plate line CP0 and the bit line XBL0. For example, when data xe2x80x9c1xe2x80x9d is to be written, a high signal is applied to the data bus line DL0 so that the ferroelectric capacitor C0 has downward polarization, and a low signal is applied to the data bus line XDL0 so that the ferroelectric capacitor C1 has upward polarization. When data xe2x80x9c0xe2x80x9d is to be written, a low signal is applied to the data bus line DL0 so that the ferroelectric capacitor C0 has upward polarization, and a high signal is applied to the data bus line XDL0 so that the ferroelectric capacitor C1 has downward polarization.
Data read operation is performed in the following manner.
First, the bit lines BL0, XBL0, BL1 and XBL1 are precharged to a low level. Thereafter, a high voltage is applied to the word line WL0 to turn on the selection transistors Q0 and Q1, and then a high voltage is applied to the cell plate line CP0. By this application, a minute voltage difference occurs between the bit line pair BL0 and XBL0, which is amplified by the sense amplifier SA0 and output to the data bus pair DL0 and XDL0.
The read operation described above uses the fact that the capacitance value of a ferroelectric capacitor changes with the polarization value previously stored in the ferroelectric capacitor. More specifically, in the case that downward polarization has been written in the ferroelectric capacitor in the data write process, charge is generated with reversal of the polarization when a voltage is applied to the cell plate line CP0, and this increases the capacitance value. On the contrary, in the case that upward polarization has been written in the ferroelectric capacitor, no reversal of polarization occurs when a voltage is applied to the cell plate line CP0, and this decreases the capacitance value.
The bit line voltage during the read operation is determined by capacitance splitting between the capacitance of the bit line and the capacitance of the ferroelectric capacitor. Therefore, the bit line voltage is high when the ferroelectric capacitor has downward polarization, and it is low when the ferroelectric capacitor has upward polarization. When a high voltage is output from the data bus line DL0 and a low voltage is output from the data bus line XDL0 after amplification of the voltages of the bit line pair, this indicates that the ferroelectric capacitor CO has downward polarization and the ferroelectric capacitor C1 has upward polarization. Therefore, It can be decided that the stored data is xe2x80x9c1xe2x80x9d. Contrarily, when a low voltage is output from the data bus line DL0 and a high voltage is output from the data bus line XDL0, it can be decided that the stored data is xe2x80x9c0xe2x80x9d.
In the conventional semiconductor memory device, when data is read from the ferroelectric capacitor, the polarization of the ferroelectric capacitor is reversed. In other words, the data is corrupted. It is therefore necessary to rewrite the data after the read operation. The data read operation is only completed by performing rewrite of the data after the output of the data to the data bus.
If the polarization of the ferroelectric film of the ferroelectric capacitor is repeatedly reversed, the ferroelectric film becomes fatigued and degraded, causing reduction in polarization value. Therefore, the life of the ferroelectric capacitor will end after about 10 billion times of polarization reversal.
In the conventional semiconductor memory device, polarization reversal is necessary during the data read operation, in addition to during the data write operation. Therefore, the number of times of data rewrite and the number of times of data read are limited to about 10 billion in total.
In view of the above problem, the inventors of the present invention proposed a semiconductor memory device that permits increase of the number of times of read, that is, a semiconductor memory device in which data is not corrupted after the data read operation.
The semiconductor memory device having the above feature will be described with reference to FIG. 10.
FIG. 10 shows two memory cell blocks MC0 and MC1, for example, arranged in the word line direction. Each of the memory cell blocks MC0 and MC1 has four memory cells, for example, arranged in the bit line direction. The four memory cells constituting the memory cell block MC0, for example, include ferroelectric capacitors C0, C1, C2 and C3 and selection transistors Q0, Q1, Q2 and Q3 respectively connected in series. The memory cell block MC0 has a block selection transistor Q4 connected to one of common nodes, and a write transistor Q5 and a read transistor Q6 connected to the other common node. The memory cell block MC1 has a block selection transistor XQ4 connected to one of common nodes, and a write transistor XQ5 and a read transistor XQ6 connected to the other common node.
The operation of writing/reading data in/from the semiconductor memory device having the configuration described above will be described. Assume that complementary data is to be written in and read from the ferroelectric capacitors C2 and XC2, as an example.
The data write operation is performed in the following manner.
A high signal is applied to a block selection line BS, a write transistor control line RE and a selected word line WL2, to turn on the block selection transistors Q4 and XQ4, the write transistors Q5 and XQ5 and the cell selection transistors Q2 and XQ2. Contrarily, a low signal is applied to non-selected word lines WL0, WL1 and WL3, to turn off the cell selection transistors Q0, XQ0, Q1, XQ1, Q3 and XQ3.
Thereafter, when data xe2x80x9c1xe2x80x9d is to be written, a high signal is applied to a set line SET, a low signal is applied to a set line XSET, a low signal is applied to a reset line RST, and a high signal is applied to a reset line XRST. When data xe2x80x9c0xe2x80x9d is to be written, a low signal is applied to the set line SET, a high signal is applied to the set line XSET, a high signal is applied to the reset line RST, and a low signal is applied to the reset line XRST.
By the signal application described above, a set line voltage is applied to one of the electrodes of the ferroelectric capacitor C2 (and XC2) while a reset line voltage is applied to the other electrode thereof Accordingly, when data xe2x80x9c1xe2x80x9d is written, the ferroelectric capacitor C2 has rightward polarization, and the ferroelectric capacitor XC2 has leftward polarization. When data xe2x80x9c0xe2x80x9d is written, the ferroelectric capacitor C2 has leftward polarization, and the ferroelectric capacitor XC2 has rightward polarization.
Once the write operation is terminated, the set line SET and the reset line RST are set at a same potential. Thereafter, a low signal is applied to the block selection line BS, the write transistor control line RE and the selected word line WL2, to turn off the block selection transistors Q4 and XQ4, the write transistors Q5 and XQ5 and the cell selection transistors Q2 and XQ2. By this operation, the inter-electrode voltages of the ferroelectric capacitors C2 and XC2 become zero. The ferroelectric films of the ferroelectric capacitors C2 and XC2 retain their polarization state when the device is powered off in this state. This semiconductor memory device therefore serves as a nonvolatile device.
The data read operation is performed in the following manner.
A high signal is applied to the block selection line BS and the selected word line WL2, to turn on the block selection transistors Q4 and XQ4 and the cell selection transistors Q2 and XQ2. Contrarily, a low signal is applied to the non-selected word lines WL0, WL1 and WL3, to turn off the cell selection transistors Q0, XQ0, Q1, XQ1, Q3 and XQ3.
By the signal application described above, ones of the electrodes of the ferroelectric capacitors C2 and XC2 are connected to the set lines SET and XSET, respectively, while the other electrodes of the ferroelectric capacitors C2 and XC2 are connected to the gates of the read transistors Q6 and XQ6, respectively. Contrarily, the ferroelectric capacitors C0, XC0, C1, XC1, C3, XC3 are disconnected from the read transistors Q6 and XQ6.
In the state described above, when a read voltage is applied to the set lines SET and XSET, a voltage determined by capacitance splitting between the capacitance value of the ferroelectric capacitor C2 and the MOS capacitance value of the read transistor Q6 is applied to the gate of the read transistor Q6. Likewise, a voltage determined by capacitance splitting between the capacitance value of the ferroelectric capacitor XC2 and the MOS capacitance value of the transistor XQ6 is applied to the gate of the read transistor XQ6.
Since the direction of the polarization of the ferroelectric film is different between storage of data xe2x80x9c1xe2x80x9d and storage of data xe2x80x9c0xe2x80x9d, the capacitance value is different between the ferroelectric capacitors C2 and XC2. Accordingly, the gate potentials of the read transistors Q6 and XQ6, which are determined by the capacitance splitting, are different from each other. The difference in gate potential between the read transistors Q6 and XQ6 causes a change in source-drain conductance. Therefore, by amplifying this conductance change as a minute potential difference between the bit lines BL0 and XBL0 and outputting the amplified change to the data bus lines DL0 and XDL0, the stored data can be read.
Once the data read operation is terminated, the set lines SET and XSET and the reset lines RST and XRST are set at the ground potential. Thereafter, a low signal is applied to the block selection line BS and the selected word line WL2, to turn off the block selection transistors Q4 and XQ4 and the cell selection transistors Q2 and XQ2. Also, a high signal is applied to the write transistor control line RE, to turn on the write transistors Q5 and XQ5.
During the read operation, the gate potentials of the read transistors Q6 and XQ6 as floating nodes float due to a leak current from the ferroelectric capacitors C2 and XC2 and the cell selection transistors Q2 and XQ2. The floating node potential is however reset at a RST potential by the operation performed after the data read.
The polarization will not be reversed between before and after the read operation by setting the read voltage applied to the set lines SET and XSET so that the voltage applied to the ferroelectric capacitors C2 and XC2 during the read operation does not exceed a resistive voltage of the ferroelectric film. This eliminates the necessity of rewrite operation, and thus the number of times of read can be increased.
The semiconductor memory device shown in FIG. 10 can read data without corrupting the data as described above. However, since the semiconductor memory device stores complementary data in memory cells that belong to two memory cell blocks, that is, adopts the 2T2C structure, it has the problem that the area of the memory cells is large.
An object of the present invention is providing a semiconductor memory device in which the area of memory cells is reduced.
The semiconductor memory device of the present invention includes at least three memory cell blocks arranged in a word line direction, each of the at least three memory cell blocks including a plurality of memory cells arranged in a bit line direction, each of the plurality of memory cells including a ferroelectric capacitor for storing data by displacement of polarization of a ferroelectric film and a selection transistor connected to one of paired electrodes of the ferroelectric capacitor, wherein each of the at least three memory cell blocks includes: a bit line, a sub-bit line and a source line extending in the bit line direction; and a read transistor having a gate connected to one end of the sub-bit line, a source connected to the source line, and a drain connected to one end of the bit line, the read transistor reads data by detecting the displacement of the polarization of the ferroelectric film of the ferroelectric capacitor of a data read memory cell from which data is read among the plurality of memory cells, and the sub-bit lines of two memory cell blocks among the at least three memory cell blocks are connected to each other via a sub-bit line coupling switch.
According to the semiconductor memory device of the present invention, the other ends of the sub-bit lines belonging to any two memory cell blocks among the at least three memory cell blocks are connected to each other via the sub-bit line coupling switch. Therefore, the memory cell blocks connected to each other via the sub-bit line coupling switch together function as a reference potential generator. By writing reference data xe2x80x9c1xe2x80x9d in a memory cell belonging to one of the two memory cell blocks and reference data xe2x80x9c0xe2x80x9d in a memory cell belonging to the other memory cell block, a reference voltage can be generated based on the reference data written in these two memory cells. By comparing the voltage between the paired electrodes of the ferroelectric capacitor of a memory cell belonging to a memory cell block different from the memory cell blocks used for generation of the reference voltage with the reference voltage, data stored in the ferroelectric capacitor of the memory cell can be read. In this way, memory cells each essentially composed of one ferroelectric capacitor and one selection transistor, that is, memory cells of a 1T1C structure are realized. The number of components constituting the 1T1C memory cell can be reduced compared with the 2T2C memory cell. Therefore, the area of the memory cells can be reduced.
In the semiconductor memory device of the invention, preferably, each of the at least three memory cell blocks includes a reset line extending in the bit line direction, and the sub-bit line is connected to the reset line via a reset switch.
By the arrangement described above, a desired voltage can be applied from the reset line to the sub-bit line. Therefore, the potential of the sub-bit line can be reset before and after data read operation.
If one end of the sub-bit line is not connected to the reset line via the reset switch, a write voltage must be applied from the well of the read transistor to the electrode of the ferroelectric capacitor via the gate capacitance, to write data in the ferroelectric capacitor. This requires a large write voltage.
According to the present invention, in which a desired voltage can be applied from the reset line to the sub-bit line, a write voltage can be applied from the reset line to the electrode of the ferroelectric capacitor. Therefore, the write voltage can be reduced.
When the semiconductor memory device of the invention includes a reset line, the reset line and the source line are preferably the same line.
By the arrangement described above, the area of the memory cell blocks can be reduced.
When the semiconductor memory device of the invention includes a reset line, two memory cell blocks adjacent in the word line direction among the at least three memory cell blocks preferably share the reset line.
By the arrangement described above, the area of the memory cell blocks can be reduced.
In the semiconductor memory cell of the invention, the other electrodes of the ferroelectric capacitors of memory cells arranged in the word line direction among the plurality of memory cells belonging to the at least three memory cell blocks preferably constitute a common electrode extending in the word line direction.
The above arrangement eliminates the necessity of placing an electrode isolating area between every adjacent memory cells, and thus the area of the memory cell blocks can be reduced.
The drive method for a semiconductor memory device of the present invention is a drive method for the semiconductor memory device described above. The method includes the steps of: writing reference data xe2x80x9c1xe2x80x9d in one of two memory cells adjacent to each other in the word line direction, while writing reference data xe2x80x9c0xe2x80x9d in the other memory cell, the two memory cells belonging to two memory cell blocks of which the sub-bit lines are connected to each other via the sub-bit line coupling switch among the at least three memory cell blocks; determining a reference voltage from a voltage between the paired electrodes of the ferroelectric capacitor of the memory cell in which the reference data xe2x80x9c1xe2x80x9d has been written and a voltage between the paired electrodes of the ferroelectric capacitor of the memory cell in which the reference data xe2x80x9c0xe2x80x9d has been written; and reading the data stored in the ferroelectric capacitor of the data read memory cell among the plurality of memory cells belonging to a memory cell block different from the two memory cell blocks among the at least three memory cell blocks by comparing a voltage between the paired electrodes of the ferroelectric capacitor of the data read memory cell with the reference voltage.
The reference data xe2x80x9c0xe2x80x9d and the reference data xe2x80x9c1xe2x80x9d may be written, not only in two memory cell blocks, but also in a number of memory cell blocks.
According to the drive method for a semiconductor memory device of the present invention, voltage change can be performed for the charge generated from the memory cell storing the reference data xe2x80x9c0xe2x80x9d and the memory cell storing the reference data xe2x80x9c1xe2x80x9d with capacitive loads of the sub-bit lines and the read transistors of the memory cell blocks to which these memory cells belong. In other words, the potential of the sub-bit lines to which the memory cells storing the reference data are connected is set at a median value between the sub-bit line potential generated based on data xe2x80x9c1xe2x80x9d and the sub-bit line potential generated data xe2x80x9c0xe2x80x9d. This median value can be used as the reference voltage. By comparing the voltage between the paired electrodes of the reference capacitor of a memory cell belonging to a memory cell block to which no memory cell storing reference data belongs with the reference voltage, data stored in the reference capacitor can be read. In this way, a memory cell essentially composed of one ferroelectric capacitor and one selection transistor, that is, a memory cell of a 1T1C structure can be achieved. The number of components constituting the 1T1C memory cells can be reduced compared with the 2T2C memory cells. Therefore, the area of the memory cells can be reduced.
In particular, by storing reference data in a memory cell belonging to a memory cell block located near the memory cell block to which the memory cell storing data belongs, it is possible to reduce a variation in property caused by the positions of the ferroelectric capacitors on the substrate and a variation in property caused by the positions of the transistors on the substrate. Thus, stable operation of the 1T1C structure, which is conventionally difficult, can be achieved.
In the drive method of the invention, preferably, each of the at least three memory cell blocks includes a reset line extending in the bit line direction, and the sub-bit line is connected to the reset line via a reset switch, the step of reading the data includes the steps of: connecting one of the paired electrodes of the ferroelectric capacitor of the data read memory cell to the sub-bit line by turning on the selection transistor of the data read memory cell, connecting the sub-bit line to the reset line by turning on the reset switch, and in this state, applying a reset voltage to the reset line; disconnecting the sub-bit line from the reset line by turning off the reset switch; and reading the data by applying a read voltage to the other electrode of the ferroelectric capacitor of the data read memory cell in the state that the sub-bit line is disconnected from the reset line.
By the method described above, a read voltage can be applied after resetting of the potential of the sub-bit line to which the data read memory cell is connected. This enables stable read operation.
In the drive method of the invention, preferably, each of the at least three memory cell blocks includes a reset line extending in the bit line direction, and the sub-bit line is connected to the reset line via a reset switch, the drive method further includes, after the step of reading the data, the steps of: connecting one of the paired electrodes of the ferroelectric capacitor of the data read memory cell to the sub-bit line by turning on the selection transistor of the data read memory cell, connecting the sub-bit line to the reset line by turning on the reset switch, and in this state, applying a reset voltage to the reset line; and disconnecting the sub-bit line from the reset line by turning off the reset switch.
By the method described above, the potential of the sub-bit line to which the data read memory cell is connected can be reset after the data read from the data read memory cell. This prevents an occurrence that data may be destroyed due to an unwanted voltage remaining in the storage node, and thus enables stable data retention.
In drive method of the invention, preferably, the step of reading the data includes the steps of: reading the data by applying a read voltage to the other electrode of the ferroelectric capacitor of the data read memory cell; and removing the read voltage applied to the other electrode of the ferroelectric capacitor of the data read memory cell, wherein the read voltage is set at a level of value with which the direction of the polarization of the ferroelectric film of the ferroelectric capacitor of the data read memory cell resumes the original direction before the data is read when the read voltage is removed.
By the method described above, no rewrite operation is required after the data read. This increases the number of times by which data can be read.
In the drive method of the invention, preferably, the read voltage is set at a level of value greater than a detection limit of a comparator comparing the voltage between the paired electrodes of the ferroelectric capacitor of the data read memory cell with the reference voltage and smaller than a resistive electric field between the paired electrodes of the ferroelectric capacitor of the data read memory cell.
By the method described above, the read voltage can be reliably set at a level of value with which the displacement of the polarization of the ferroelectric film of the ferroelectric capacitor of the data read memory cell resumes the original displacement before the data read when the read voltage is removed.
In the drive method of the invention, preferably, each of the at least three memory cell blocks includes a reset line extending in the bit line direction, and the sub-bit line is connected to the reset line via a reset switch, the drive method further includes the step of: writing data in the ferroelectric capacitor of a data write memory cell among the plurality of memory cells belonging to the at least three memory cell blocks, the step of writing data includes the step of: connecting one of the paired electrodes of the ferroelectric capacitor of the data write memory cell to the sub-bit line by turning on the selection transistor of the data write memory cell, connecting the sub-bit line to the reset line by turning on the reset switch, and in this state, applying a write voltage corresponding to binary data between the other electrode of the ferroelectric capacitor of the data write memory cell and the reset line.
By the method described above, data can be written with a low write voltage.
In the drive method of the invention, preferably, the absolute of the write voltage when the binary data is data xe2x80x9c0xe2x80x9d is different from the absolute of the write voltage when the binary data is data xe2x80x9c1xe2x80x9d.
By the method described above, the reliability of the semiconductor memory device can be improved.